Phase Lock Oscillators aid in the recovery of data previously stored at discrete time intervals. In many instances the original storage process or later recovery process are not perfectly timed. As a result, a recovered data pulse may not occur at the proper time window. When this occurs, it is necessary to adjust the recovery time windows so that the recovered data pulse occurs during the proper discrete time window, thereby duplicating the data as originally stored.
Phase Lock Oscillators typically include a voltage controlled oscillator which produces the time windows. Other circuitry in the Phase Lock Oscillators shift the position of the time windows so that the recovered data pulse falls into the proper time window. Ideally, when a data pulse occurs within a particular time window it duplicates the original data. If a data pulse falls into the wrong time window an error results. In order to prevent such errors the time windows and the discrete time intervals are synchronized. If the time windows are not synchronized with the discrete time intervals, the pulse may fall into the wrong time window resulting in a read error. Before data is read, a number of uniformly spaced pulses are provided to allow the Phase Locked Oscillator Circuit to shift the time windows so they are in synchronization with the discrete time intervals.
The uniformly spaced pulses are referred to as the PLO sync zone, and are usually recorded at the header of a track or track sector. The process of the Phase Lock Circuit synchronizing the time windows to the discrete time intervals is referred to as locking on. Under some circumstances, presently available Phase Locked Oscillator Circuits function as designed but are unable to synchronize the time windows and the discrete time intervals during the PLO sync zone. For example, in the presence of jitter, when the even pulses occur slightly after the discrete time interval and the odd pulses occur slightly before the discrete time interval, some Phase Lock Oscillator Circuits perform as designed yet produce a continuous pattern of read errors.
One solution to enable the PLO circuit to lock on in the presence of jitter or other similar situations is to phase lock on every other pulse. However, this produces the undesirable result of increasing the normal phase lock on time due to loss of loop gain in the Phase Lock Oscillator Circuit. When the lock on time increases the length of the PLO sync zone increases thereby decreasing the amount of memory space available on the media for data.
Thus, there is a need for a Phase Lock Oscillator Circuit that will quickly synchronize the time windows with the discrete time intervals in the presence of jitter and similar conditions while maintaining the loop gain of the circuit.